LSK170 [Linear Systems]

ULTRA LOW NOISE SINGLE N-CHANNEL JFET; 超低噪声单N沟道JFET


型号：	LSK170
厂家：	Linear Systems
描述：	ULTRA LOW NOISE SINGLE N-CHANNEL JFET 超低噪声单N沟道JFET
文件：	总1页 (文件大小：116K)
中文：	中文翻译
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LSK170

ULTRA LOW NOISE

Linear Integrated Systems

SINGLE N-CHANNEL JFET

FEATURES

ULTRA LOW NOISE (f = 1kHz)

HIGH BREAKDOWN VOLTAGE

HIGH GAIN

HIGH INPUT IMPEDANCE

LOW CAPACITANCE

e_n= 0.9nV/√Hz

BV_GSS= 40V max

Y_fs= 22mS (typ)

I_G= -500pA max

22pF max

TO-92

SOT-23

BOTTOM VIEW

TOP VIEW

IMPROVED SECOND SOURCE REPLACEMENT FOR 2SK170

ABSOLUTE MAXIMUM RATINGS¹

@ 25 °C (unless otherwise stated)

D G S

1 2 3

Maximum Temperatures

Storage Temperature

-65 to +150 °C

-55 to +135 °C

Operating Junction Temperature

Maximum Power Dissipation

Continuous Power Dissipation @ +125 °C

Maximum Currents

400mW

Gate Forward Current

I_G(F)= 10mA

*For equivalent monolithic dual, see LSK389 family.

Maximum Voltages

Gate to Source

Gate to Drain

V_GSS= 40V

V_GDS= 40V

ELECTRICAL CHARACTERISTICS @ 25 °C (unless otherwise stated)

SYMBOL

BV_GSS

V_GS(OFF)

V_GS

CHARACTERISTIC

MIN TYP MAX UNITS CONDITIONS

Gate to Source Breakdown Voltage

Gate to Source Pinch-off Voltage

Gate to Source Operating Voltage

V_DS= 0, I_D= 100µA

V_DS= 10V, I_D= 1nA

V_DS= 10V, I_D= 1mA

0.2

0.5

LSK170A

LSK170B

LSK170C

2.6

6.5

0.5

Drain to Source Saturation

Current

I_DSS

V_DG= 10V, V_GS= 0

I_G

Gate Operating Current

V_DG= 10V, I_D= 1mA

V_DG= 10V, V_DS= 0

V_GD= 10V, V_GS= 0, f = 1kHz

V_DG= 15V, I_D= 1mA

I_GSS

Y_fss

Y_fs

Gate to Source Leakage Current

Full Conduction Transconductance

Typical Conduction Transconductance

V_DS= 10V, I_D= 2mA, f = 1kHz,

e_n

Noise Voltage

0.9

2.5

1.9 nV/√Hz

NBW = 1Hz

V_DS= 10V, I_D= 2mA, f = 10Hz,

nV/√Hz

NBW = 1Hz

C_ISS

C_RSS

Common Source Input Capacitance

Common Source Reverse Transfer Cap.

V_DS= 15V, I_D= 500µA

Absolute maximum ratings are limiting values above which serviceability may be impaired.

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rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.